发明名称 PLL CIRCUIT
摘要 PURPOSE:To obtain a clock matching with the accuracy of a signal to be sent by operating a voltage controlled oscillator through the selection of a crystal oscillator or a CR oscillator depending on the accuracy of an input signal. CONSTITUTION:As soon as a control circuit C started by a lock signal of a 1st phase comparator (PD) 1 of a 1st PLL circuit A in a 2PLL circuit B selects a voltage controlled crystal oscillator section E comprising a 3rd low pass filter (LPF) 9 and a 3rd voltage controlled crystal oscillator (VCXO) 10 with changeover switches 11,12; the internal timer is started to monitor the lock, signal of the 2nd PD5. When the lock signal of the 2nd PD5 is generated during the timer valid period, the current state is maintained and when the clock signal is not generated, the changeover switches 11,12 select a CR voltage controlled oscillator D. Thus, the clock with accuracy matching with the transmission signal is generated.
申请公布号 JPH03145214(A) 申请公布日期 1991.06.20
申请号 JP19890283626 申请日期 1989.10.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKEDA TADASHI
分类号 H03L7/087 主分类号 H03L7/087
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