| 摘要 |
With the circuit according to the invention, certain of the input clock signals clk(1)...clk(n) are selected to become the output clock clko of the circuit. The selected clock's pathway is connected in place while the old clock is functioning as the output clock clko. The changeover is done at the falling edge of the old clock, and the new clock is connected to the output on the falling edge of the new clock, so that the changeover does not cause spikes in the output clock. <IMAGE> |
