SERIAL DATA DIRECT MEMORY ACCESS SYSTEM

摘要

Serial data direct memory access apparatus includes a receiver circuit responsive to incoming serial data clocked at a chosen rate. The apparatus also includes computer controlled bus system with expandable memory. The bus system clocking is at a higher rate than the rate of the incoming data. The incoming serial data is converted to parallel data words and addresses are formed and assigned to each data word. Receiver circuits also provide means for transferring the converted parallel data to the assigned address locations of memory in the bus system. When the receiver circuit is accessing memory, the bus system computer which normally manages the memory is put to sleep.