发明名称 PHASE LOCKED LOOP CIRCUIT AND DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To form a phase locked loop circuit operated always stably by selected the time width of a 1st pulse signal to be a half of one period of the output signal of a voltage controlled oscillator in a phase locked loop circuit having the voltage controlled oscillator, a phase comparator and a filter. CONSTITUTION:An output signal Tc goes to an H level at the rise of an input pulse signal 100 and goes to an L level at the fall of an inverting output signal 300 coming succeedingly. Simultaneously a TS signal goes to H in this timing and the output signal Tc goes to an L level at the rise of an output signal 200 coming succeedingly. When a phase comparator 21 is operated in such a manner, the pulse width of signals TS, TD is a half the output signal period independently of the duty of the output signal 200 and the inverting output signal 300. Thus, the output current characteristic of a smooting filter 12 with respect to the phase difference between the input pulse signal 100 and the output signal 200 is stable independently of the duty of the output signal of the voltage controlled oscillator 14.
申请公布号 JPH03143116(A) 申请公布日期 1991.06.18
申请号 JP19890282749 申请日期 1989.10.30
申请人 HITACHI LTD 发明人 HOTTA RYUTARO;MIYAZAWA SHOICHI;HASE KENICHI;KOJIMA SHINICHI
分类号 H01L27/088;H01L21/8234;H03L7/085;H03L7/093 主分类号 H01L27/088
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