| 摘要 |
PURPOSE:To obtain a large scale finite state machine without reducing the action speed despite increase of the number of PLA stages by adding at least 1st and 2nd PLAs of different sharing ranges of control to a controller together with a control logic circuit which controls these PLAs. CONSTITUTION:A PLA 24 can be synchronous with the PLA 21 - 23. That is, under such conditions, the PLA 24 is first set in an active state and outputs a synchronism request signals 24-S. Then the presence or absence of a synchronizing signal 22-S2 received from the PLA 22 is checked. When the absence of the signal 22-S2 is confirmed, an output fixing signal 5-S is outputted to the PLA 24. Thus the control output 24-S1 of the PLA 24 is held in a fixed state. When the PLA 22 is activated, the signal 22-S2 is produced from the PLA 22. Thus a control logic circuit 5 stops the output of the signal 5-S. As a result, the output fixed state of the PLA 24 is canceled and the PLA 24 is driven synchronously with the PLA 22. |
