发明名称 Peak level detection circuit
摘要 A peak level detection circuit provided with a peak holding unit used for determining the threshold level for discrimination of the logics "1" and "0" of the received data from the peak level of the received data signals, wherein even if after a first input pulse train with a peak level of Vin1 is received, a second input pulse train having a peak level of Vin2 lower than Vin1 is received, it is made possible to immediately discriminate the logics "1" and "0" of the second input pulse train by detecting the appearance of the second input pulse train, then immediately pulling down the Vin1 which is held.
申请公布号 US5025176(A) 申请公布日期 1991.06.18
申请号 US19900472151 申请日期 1990.01.30
申请人 FUJITSU LIMITED 发明人 TAKENO, MINORU
分类号 G01R19/04;H03K5/08 主分类号 G01R19/04
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