发明名称 POWER-ON RESET CIRCUIT
摘要 <p>PURPOSE:To surely reset a circuit despite the change of a time constant caused to the rise of a power supply by outputting a reset signal after detecting the power voltage with which an element is completely stabilized after application of the power supply. CONSTITUTION:The power voltage with which a voltage comparator 6 outputs an inverted signal is set at a level where an element is stabilized. Thus, the inverted output can be used as a reset signal. That is, a reset signal is outputted with the voltage of a power supply 7 based on the difference potential between the resistance dividing voltage equivalent to the variable resistance obtained by a MOS transistor 1, a MOS transistor 2, and resistor 3 and the resistance dividing voltage obtained by the resistors 4 and 5. Thus, it is possible to solve such a problem where a circuit could not be reset when the rise time constant of the power supply 7 exceeds the time constant set by the resistor and a capaci tor.</p>
申请公布号 JPH03141415(A) 申请公布日期 1991.06.17
申请号 JP19890278520 申请日期 1989.10.27
申请人 NEC CORP;NEC ENG LTD 发明人 KURAISHI YOSHIAKI;INAMI DAIJIRO;SESHIMO YOICHI;KITAMURA YOSHIAKI
分类号 G06F1/24 主分类号 G06F1/24
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