| 摘要 |
PURPOSE:To increase the speed of a floating point reciprocal calculation with a small amount of hardware by switching and using a two's complement circuit, an upper bit inversion circuit, a 1-bit left shifter, etc., for a floating decimal point reciprocal root calculation. CONSTITUTION:A fixed point multiplier 5 executes the calculation of the output of selection circuits 3, 4, and a two's complement circuit 6 executes the two's complement calculation of two to the output of the fixed point multiplier 5. An upper bit inversion circuit 7 executes the bit inversion of a most significant bit and upper three bits, a 1-bit left shifter 8 executes a 1-bit left shift, and a register 9 stores that output. A two's complement circuit 10 of an exponent part 2 executes the two's complement calculation of 2 to the exponent part output of the register 1, and an exponent part adder 11 executes the addition 1 or 2 of that output. A reciprocal square root output, which has that output as the exponent part, and has the output of the 1-bit left shifter 8 as the mantissa part, is stored at a register 12. Thus, the speed of calculation is increased. |
