| 摘要 |
<p>A mutual division circuit includes a single mutual division unit or a plurality of cascaded mutual division units for dividing a polynomial including a first input polynomial Ri-1(X) as a factor by a second input polynomial Qi-1(X), thereby to determine a quotient and a remainder Ri(X), determining an overall quotient lambda i(X) from the quotient and a third input polynomial lambda i-1(X), and producing the remainder Ri(X), the first input polynomial Ri-1(X) or the second input polynomial Qi-1(X), and the overall quotient lambda i(X) as a first output polynomial Ri(X), a second output polynomial Qi(X), and a third output polynomial lambda i(X), respectively. The mutual division circuit also has a data selector (42) for receiving, at an input port thereof, respective initial polynomials of the first, second, and third input polynomials, and supplying output data to the single mutual division unit or a first one of the cascaded mutual division units, and a feedback or data bus (45) for supplying output data from the single mutual division unit or a last one of the the cascaded mutual division units to another input port of the data selector (42). The single mutual division unit or the cascaded mutual division units are used a plurality of times for carrying out arithmetic operations therein. <IMAGE></p> |
