| 摘要 |
PURPOSE:To slow down a signal speed subject to time division multiplex by providing a PLL circuit generating a sampling clock signal synchronously with a transmission data signal to lower the frequency of the sampling clock signal while suppressing waveform distortion. CONSTITUTION:A transmission data is inputted to a PLL circuit 4 and a sampling clock signal 5 synchronously with the transmission data signal 1 is generated and inputted to a parallel/serial conversion circuit 7. When the parallel/serial conversion circuit 7 applies time division multiplex to the transmission data signal 1, a transmission request signal 2 and a data terminal ready signal 3, the sampling is implemented by using the sampling clock signal 5 synchronously with the transmission data signal 1. Thus, waveform distortion due to the sampling is not caused. Moreover, since the sampling frequency is lowered, the, speed of time division multiplexed signal slows down and the band of the transmission line is used effectively. |
