| 摘要 |
A cascadable seventeen-bit self-testing comparator (20) is produced on a twenty-four pin GAL TM 39V18 generic array logic chip by so interconnecting the data pins (1-17) with the logic macro cells (24a-h, 26a-i), and configuring the macro cells, that any data applied to the pins is registered in the macro cells (24a-h, 26a-i) upon pulsing the clock (35), and any exact coincidence of subsequent data with the registered data causes one of the macro cells (26j) to generate a match-indicating output (61).
|
