发明名称 Vernier structure for flip chip bonded devices
摘要 PCT No. PCT/GB89/00282 Sec. 371 Date Nov. 30, 1989 Sec. 102(e) Date Nov. 30, 1989 PCT Filed Mar. 16, 1989 PCT Pub. No. WO89/08926 PCT Pub. Date Sep. 21, 1989.A flip-chip solder bonding structure having first and second components. Each component is made from a substrate haivng on one surface an array of solderable pads. Selected pads have solder bumps deposited thereon with each surface having a plurality of alignment marks formed thereon whereby when the components are positioned face to face, the arrays register with one another to enable a solder bond to be formed. The respective pluralities of alignment marks may be inspected to assess their relative positions in order to determine the accuracy of the solder bond. The solderable pads and the alignment marks on each surface are formed during the same processing stage as metallized regions. The solder bumps are applied to the metallized regions forming the alignment marks.
申请公布号 US5022580(A) 申请公布日期 1991.06.11
申请号 US19890435477 申请日期 1989.11.30
申请人 PLESSEY OVERSEAS LIMITED 发明人 PEDDER, DAVID J.
分类号 G02B6/42;H01L21/60;H01L23/544;H05K1/02;H05K3/30;H05K3/34 主分类号 G02B6/42
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