发明名称 TEST FACILITATING CIRCUIT
摘要 PURPOSE:To facilitate the formation of the test pattern of circuit operation by providing a circuit realizing the transition of state for an undefined state and an addition circuit judging whether the state of a memory element part is in the undefined state. CONSTITUTION:The transition from the initial state of a circuit to an undefined state and the transition connecting all of undefined states in a chain-like manner are performed. An addition circuit a facilitating a test and an addition circuit B having the output terminal of a memory element part (FF) 2 as an input terminal and judging whether the state realized by the FF is an undefined state to send the state realized by the FF to an external output terminal are respectively constituted of inverters 6, 7, AND circuits 8 - 10, 13, 14 and OR circuits 11, 12, 15 as shown by drawings (a), (b). The state variable value of a transition destination state is inputted to the FF to be held thereto in the circuit A but the state variable value is next inputted to the circuit B and, on the basis of the state variable at that time, it is judged whether the state realized by the FF is an undefined state. By this constitution, trouble performing the transition to the undefined state and trouble detectable only in the undefined state can be easily detected and the circuit can be tested easily at a high speed.
申请公布号 JPH03134577(A) 申请公布日期 1991.06.07
申请号 JP19890271505 申请日期 1989.10.20
申请人 FUJITSU LTD 发明人 TANAKA TSUNEO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
代理机构 代理人
主权项
地址