Data transfer apparatus.

摘要

A data transfer apparatus wherein a signal for permitting or inhibiting transmission of data is outputted from a master microprocessor to a slave microprocessor, and upon simultaneous generation of outgoing data in both microprocessors, even if the master microprocessor is placed in a reception ready state, the slave microprocessor recognizes it as a transmission request signal unless receiving a transmission permit signal, so that the slave microprocessor is set in a data reception ready state instead of transmitting the data. Therefore, data transmission from the master microprocessor alone is performed in such a case to consequently prevent collision of the respective data on a bidirectional data bus.