发明名称 CONTROL CIRCUIT FOR NOISE SEQUENCER
摘要 PURPOSE:To attain continuous sounding of a test signal by applying forcibly a clock signal to an input buffer circuit when it is detected that an output signal of an output buffer circuit is in the state of S channel. CONSTITUTION:An output buffer circuit 11 comprising 3rd-6th D-FF 7-10 is provided, which outputs an output signal of a decode circuit 6 decoding an output signal of an input buffer circuit 6 comprising 1st and 2nd D-FF 3, 4 in response to a 1st frequency divider output signal Q1 of a frequency divider circuit 2. Moreover, a selection circuit 14 is provided, which selects any of the 1st frequency divider output signal Q1 of the frequency divider circuit 2, its inverse of Q1 and a 2nd frequency divider output signal in response to an output signal of an AND gate 13 receiving a Q3 output of the 3rd D-FF 7 and an output control signal of a switch 12. Then a control signal driving a noise sequencer is obtained from an output terminal of the output buffer circuit 11. Thus, the test signal is continuously sounded.
申请公布号 JPH03132299(A) 申请公布日期 1991.06.05
申请号 JP19890270618 申请日期 1989.10.18
申请人 SANYO ELECTRIC CO LTD 发明人 MEYA MASATO;ISHIKAWA TSUTOMU;ARAI MASASHI
分类号 H04S7/00 主分类号 H04S7/00
代理机构 代理人
主权项
地址