| 摘要 |
PURPOSE:To prevent pseudo locking occurring and to perform a stable operation by inserting a nonlinear type amplifier to the output of a frequency deviation detection circuit. CONSTITUTION:The phase locked circuit is comprised in such a way that the output (h) of a first phase error detection circuit 4 is applied as a delayed signal Hh' via a delay device 201 when it is inputted to a synthesis circuit 6, and also, that the output (l) of an LPF 8 is inputted via the nonlinear type amplifier 202 when the synthetic output (j) of the synthesis circuit 6 is applied to the second control terminal 10 of a VCO 3 via the LPF 8. In such a case, the output (l) of the LPF 8 shows linearity similarly as in a conventional circuit, however, characteristic l' can be obtained by passing the nonlinear type amplifier 202. The voltage-to-frequency sensitivity of the characteristic l' is varied in the neighborhood of a clock frequency f0 and another pseudo locking point. Thereby, it is possible to make the pseudo locking hard to occur and to continue the stable operation when it is locked to the clock frequency f0. |
