发明名称 Matrix arithmetic circuit.
摘要 A matrix arithmetic circuit includes an address generator (7), a first multiplier (1), a second multiplier(2), and an accumulator (3)The address generator (7) generates addresses of first, second, and third memories (4,5.6) to read out matrix elements from the first, second, and third memories at predetermined timings. The first multiplier (1) multiplies the first and second matrices. The second multiplier (2) multiplies the multiplication result from the first multiplier (1) and the third matrix. The accumulator (3) accumulates the multiplication result from the second multiplier (2) to obtain an arithmetic result. <IMAGE>
申请公布号 EP0430181(A2) 申请公布日期 1991.06.05
申请号 EP19900122670 申请日期 1990.11.27
申请人 NEC CORPORATION 发明人 KANOH, TOSHIYUKI, C/O NEC CORPORATION
分类号 G06F17/10;G06F17/16 主分类号 G06F17/10
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