| 摘要 |
PURPOSE:To prevent the mixing of noises and a malfunction due to currents of an internal logic gate by using a separate system as the power supply of an input buffer and the internal logic gate. CONSTITUTION:A NOR gate composed of P channel MOS transistors P1, P2 and N channel MOS transistors N1, N2 represents an input buffer circuit, an input terminal IN is connected to a bonding pad for an input, and another input CONT represents a control input from internal logic gates. An output from the NOR gate is input to an inverter consisting of P3 and N3 at a CMOS level, and an output from the inverter is buffered by inverters at two stages made up of P4 and N4 and P5 and N5, and connected to the internal logic gates. The gate bonded with a power supply V1 and a ground wiring G1 thereof in these gates is shaped only in the NOR gate, and the logic gates after an inverter at the next stage is connected to a power supply V2 and a ground wiring G2 thereof. |
