发明名称 Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
摘要 The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.
申请公布号 US5021848(A) 申请公布日期 1991.06.04
申请号 US19900492113 申请日期 1990.03.13
申请人 CHIU, TE-LONG 发明人 CHIU, TE-LONG
分类号 H01L27/115 主分类号 H01L27/115
代理机构 代理人
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