| 摘要 |
<p>PURPOSE: To utilize input/output ports in a packet switch by providing an addressable storage device in each of plural input ports, and allowing an output port to address the input port for obtaining a packet. CONSTITUTION: Each input port 104 operates interface connection with a data bus(DBUS), address bus(ABUS), and transmission bus(TBUS) of a packet interconnection 103 in a synchronizing base. Each output port 110 operates interface connection with the data bus(DBUS), address(ABUS), scheduler bus(SBUS), and total quanta bus(TQBUS) of the packet interconnection 103 in the synchronizing base. A scheduler 113 controls the path selection of a packet from the input port 104 to the output port 110 and a statistical port 116 cooperatively with a processor 114.</p> |
