| 摘要 |
A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and data concerning the access, etc.) as is made by the operation processing block when the clock signal is stopped, and to what clock of that access cycle the bus access proceeds. The stop control block controls the bus arbitration block to electrically disconnect the processor module from the bus. After the restart of supplying the clock signal, the bus arbitration block, the bus access control block, the address output block and the data input/output block are restored on the basis of the contents of the bus access. Then the bus access that was stopped is resumed from its beginning. When the number of clocks of the clock signal is equal to that stored in the memory block after the restart of supplying the clock signal, the stop control block supplies again the clock signal to the operation processing block. Subsequently, the operation processing block continues the bus access.
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