发明名称 Input buffer circuit having a resistor for reducing through-current and a capacitor for preventing delay
摘要 An input buffer for semiconductor integrated circuits has a resistor (16), capacitor (17) and a logical gate comprising transistors (11, 12, 13) connected in series between a supply line (61) and a ground line (62). The resistor (16) reduces the through current which flows toward the ground (Vss) when the logical gate switches. In a high speed operation, the capacitor (17) supplies current to the logical gate so that any delay which may possibly be caused by the provision of the resistor (16) can be prevented.
申请公布号 US5021685(A) 申请公布日期 1991.06.04
申请号 US19900508460 申请日期 1990.04.13
申请人 MITSUBISHI DENKI KABUSHIKA KAISHA 发明人 KIHARA, YUJI
分类号 H03K19/003;H03K19/0185 主分类号 H03K19/003
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