| 摘要 |
PURPOSE:To prevent processing speed lowered without generating turbulence in pipeline processing even when a conditional branch instruction is decoded by setting a branch destination execution flag by estimating the satisfaction of a condition. CONSTITUTION:An instruction decoder part 1, when decoding the conditional branch instruction, informs it to a branch judging part 3, and the branch judging part 3 estimates the satisfaction of a condition based on information a 1 from the instruction decoder part 1 and the instruction a 3 of branch trace from a debug control part 4, and estimates the satisfaction of the branch before information a 2 from an arithmetic execution part 2 when high probability for the satisfaction of the branch exists, and generates an instruction a 4 to set a branch destination execution bit. After that, the information a 2 is received from the arithmetic execution part 2, and the judgement of a receiving condition is performed, and when no branch is satisfied, a correction instruction a 5 is issued to the debug control part 4. Thereby, it is possible to to prevent the processing speed lowered without generating the turbulence in the pipeline processing even when the conditional branch instruction is decoded. |
