| 摘要 |
PURPOSE:To enable highly efficient design of a high density DRAM array and to reduce the number of sense amplifier and the chip area by activating a bipolar transistor, at the time of read out, and operating a DRAM cell as a gain cell with a reverse base current. CONSTITUTION:A capacitive load exists between the base and the emitter. When the base voltage VBE is in the range of 0V<VBE<0.45V, charges stored in the load flow through the base to the emitter and the voltage VBE across the load drops and approaches to 0V. When the base voltage VBE is in the range of 45V<VBE<0.87V, the load is charged by the reverse base current and thereby the voltage VBE across the load increases and approaches to 0.87V. When VBE>0.87V, positive base current flows through the base to the emitter and thereby the voltage VBE across the load drops and approaches to 0.87V. Since the VBE is maintained at 0V or 0.87V, self amplifying function can be provided when the voltage is maintained. Consequently, a memory is constituted with a bipolar transistor through utilization of voltage holding function. |
