发明名称 INSPECTION INPUT GENERATING METHOD AND EASY INSPECTION DESIGN METHOD
摘要 PURPOSE:To reduce calculation time and and the area of a chip by recognizing a register which makes the generation of inspection input hard in the middle way of generating the inspection input, and replacing the register by a scan register. CONSTITUTION:A scan request times critical value is designated to each register, and the generation of the inspection input which propagates the influence of a fault selected by using algorithm in which known circuit topology is used to the external output pin of a circuit is performed. At such a case, for example, when a value exceeds the limiting value of the number of times of an operation repeating the re-setting of the value to an external input pin to detect one fault, inspection input generating processing for the fault is interrupted, and the number of times of scan request of the register in which the fault can be detected by performing scan is updated. And the register with the critical value exceeding the number of times of scan request is recognized, and the register is replaced by the scan register, and after that, the next processing for the fault is performed on a changed circuit. In such a way, the calculation time and the number of additional hardware can be reduced.
申请公布号 JPH03129438(A) 申请公布日期 1991.06.03
申请号 JP19900180001 申请日期 1990.07.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HOSOKAWA TOSHINORI;MOTOHARA AKIRA
分类号 G01R31/317;G01R31/28;G01R31/3185;G06F11/22;G06F17/50 主分类号 G01R31/317
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