DELAY CIRCUIT

摘要

PURPOSE:To reduce the influence of delay time fluctuation caused by power supply voltage fluctuation and manufacture process fluctuation by adding an operational amplifier and a voltage generating means and canceling the fluctuation of the power supply voltage and the fluctuation in the threshold value voltage of a logic circuit with the power supply voltage fluctuation by the charging or discharging current of a second MOS field effect transistor. CONSTITUTION:For a second MOS field effect transistor M2, the drain is guided by the drain of a first MOS field effect transistor M1 and the source is guided through a resistor Rc to another power supply line. A direct current voltage to be supplied to the non-inverted input terminal of an operational amplifier A1 is outputted from the voltage generating means composed of a logic circuit Q2, which is equal with a logic circuit Q1, and operational amplifiers A2 and A3 and obtained by calculating the threshold value voltage and the power supply voltage of the Q2. The A1 biases the gate and the source of the M2 so that a voltage on one end side of the resistor Rc can be equal with this direct current voltage. Consequently, the discharging current or the charging current to flow to the M2 is determined by a ratio between the direct current voltage and the resistance value of the Rc and the fluctuation of the power supply voltage and the threshold value voltage fluctuation of the logic circuit Q1 with this fluctuation are canceled.