发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To check the delay time of a combinatorial circuit part at time intervals of the timing pulse, by giving the value of a latch to the combinatorial circuit through an exclusive OR circuit. CONSTITUTION:An exclusive OR circuit group 13 is connected to the input part of a part to be diagnosed; and in the normal operation, the signal passing through a combinatioral circuit 1 is taken into a latch group 2, a latch group 3, and a latch group 5 at a latch timing 8, a latch timing 9, and a latch timing 10 respectively. In respect to the diagnosis of a combinatorial circuit 4, a pattern obtained by inverting the original test pattern is written to latch groups 2 and 3 in order by a scan address 11 and scan-in data 12. Pulses are inputted instead of latch timings 8 and 9 from diagnostic terminals 14 and 15 and are caused to pass through the combinatorial circuit 4 and are taken into the latch group 5 at the latch timing, thus checking the circuit.
申请公布号 JPS57130156(A) 申请公布日期 1982.08.12
申请号 JP19810014325 申请日期 1981.02.04
申请人 HITACHI SEISAKUSHO KK 发明人 IGARASHI TOSHIO
分类号 G01R31/28;G01R31/3185;G06F11/22 主分类号 G01R31/28
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