| 摘要 |
<p>PURPOSE:To easily adjust a fine delay time by providing a transfer gate to each of plural resistors connected in series in a form of parallel connection. CONSTITUTION:The delay circuit is provided with plural resistors 31, 32 connected in series and the resistors 31, 32 are provided respectively with transfer gates 61, 62 connected in parallel with the resistors 31, 32. Thus, the delay time when both the two transfer gates are turned off is twice the delay time when either of the transfer gates 61, 62 is turned on. When both the transfer gates 61,62 are turned on, since the resistors 31, 32 are short-circuited by the gates, the combined resistance is '0'. Thus, the delay time in this case is far smaller than the delay time when either of the transfer gates 61, 62 is turned on. Thus, fine adjustment of the delay time is attained.</p> |
