发明名称 NOTCH ELIMINATOR FOR MATRIX DATA
摘要 PURPOSE:To obtain a notch eliminator for matrix data with simple constitution, miniaturized, with low cost, easy to handle, and with high reliability by using a decoder, a selector, and an exclusive OR circuit. CONSTITUTION:The decoder 10 outputs an all-high decode signal D1 when all inputted reference item signals A11-A33 are set at high levels, while, outputs an all-low decode signal Do when they are set at low levels. Then, the selector 20 selects the all-high decode signal D1 when a remarked item signal SEL is set at the low level, and selects the all-low decode signal Do when it is set at the high level, then, inputs them to the exclusive OR circuit 40. The remarked item signal SEL is also inputted to the exclusive OR circuit 40. Therefore, a correction data signal D in which the remarked item signal SEL is inverted is outputted from the exclusive OR circuit 40 when the remarked item signal SEL is opposite to all the reference item signals A11-A33, and no signal D is outputted in other cases. Thereby, the notch eliminator for matrix data with simple constitution, easy to handle, miniaturized, and with low cost is obtained.
申请公布号 JPH03126178(A) 申请公布日期 1991.05.29
申请号 JP19890264568 申请日期 1989.10.11
申请人 TOKYO ELECTRIC CO LTD 发明人 ONO SHUNICHI
分类号 G06T5/20 主分类号 G06T5/20
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