LATERALE DMOS-FET-VORRICHTUNG MIT REDUZIERTEM BETRIEBSWIDERSTAND

摘要

A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.