Semiconductor memory device having input/output data signal lines propagating data bit at high-speed regardless of fluctuation in power voltage signal.

摘要

A semiconductor memory device comprises a plurality of memory cells (M11 to Mmn) arranged in rows and columns, a plurality of bit line pairs (BLP1 to BLPn) respectively coupled to the columns of the memory cells, a plurality of word lines (W1 to Wm) respectively coupled to the rows of the memory cells and selectively activating the memory cells for producing small differences in voltage level on the plurality of bit line pairs, respectively, a plurality of sense amplifier circuits (SA1 to SAn) respectively coupled to the plurality of bit line pairs and selectively coupling component bit lines of the bit line pairs to first and second voltage sources depending upon the small differences, first and second data signal lines (44a and 44b), a column selector circuit (43) interconnecting the first and second data signal lines and one of the plurality of bit line pairs, and a pull-up circuit (46) coupled between the first voltage source and the first and second data signal lines for allowing voltage levels on the first and second data signal lines to vary within a predetermined voltage range, wherein a small current path (Q41) is coupled between the first and second data signal lines and causes the voltage level on one of the first and second data signal lines to follow the voltage level on the other of the first and second data signal lines upon fluctuation in voltage level at the first voltage source.