Phase detector suitable for use in phase lock loop.

摘要

A digital phase detector comprises a first input (V) for receiving an output of a voltage controlled oscillator (10) and a second input (R) for receiving a reference signal. When a phase of the first input is in advance of that of the second input or when a frequency of the first input is higher than that of the second input, the phase detector operates to output a first control signal (D) for decrease of an oscillation frequency of the voltage controlled oscillator (10). When the phase of the first input is delayed from that of the second input or when the frequency of the first input is lower than that of the second input, the phase detector operates to output a second control signal (U) for increase of the oscillation frequency of the voltage controlled oscillator (10). In addition, the phase detector is configured to output neither the first control signal nor the second control signal when both of the first input and the second input are at a low level.