| 摘要 |
PURPOSE:To improve the resolution of the setting of a low frequency by using a multiplication unit processing a signal in a way of fixed decimal point and processing a coefficient in terms of the floating method for a multiplier. CONSTITUTION:A multiplier multiplies a coefficient alpha with an inputted signal D and outputs the result and consists of a multiplication circuit 21 and a bit shifter 22. As the coefficient alpha, an 8-bit data comprising a 4-bit significant figure part and a 4-bit exponent part, and as the signal D, data of a prescribed bit length such as 16 bits is inputted. A constant number '1' is supplemented to the MSB of the effective figure part of the coefficient alpha and the coefficient is converted into a binary number representing a figure of 0.5 or over and less than 1 (that is, 16/32-31/32) and fed to one input terminal A of the multiplication circuit 21. Moreover, the exponent part (n) of the coefficient alpha is fed to a shift quantity designation terminal (n) of the bit shifter 22 and the exponent part (n) designates a negative bit shift (shift down) quantity. Thus, the resolution in the setting of a low frequency is improved. |
