CELL SYNCHRONIZATION CIRCUIT

摘要

PURPOSE:To attain high speed operation and to facilitate circuit integration by applying serial parallel conversion to a received serial data string into a parallel data and applying pipeline processing form CRC calculation to the obtained parallel data. CONSTITUTION:A serial parallel conversion circuit 1 converts a received serial data string into a j-bit parallel data and outputs the result. A delay circuit 2 delays the output of the circuit 1 by one clock by using 1/j clock. A shift matrix 3 receives outputs of the circuits 2, 1 to output a j-bit parallel data. A CRC arithmetic circuit 4 applies CRC partial calculation by using j-bit outputted from the matrix 3 and inputs obtained m-set of outputs to m-set of FFs of the 1st stage by using 1/j clock signals respectively. Moreover, the CRC partial calculation is implemented sequentially and the output of the k-th stage FF being the final stage of the circuit 4 is fed to an OR circuit 5. The output of the circuit 5 is given to a frame counter 11 via a frame synchronization protection circuit 8, the counter 11 is operated by a 1/j clock to output a frame pulse.