| 摘要 |
The present invention relates to PLA consisting of pairs of cells equipped with pre-load and memory storage means. Each cell comprises, between a result line (LMj; LSi) and earth, input transistors in parallel (MN1) in series with a second transistor (MN2). The result lines are linked to the power supply via a third transistor (MP3) and to the input of an inverter (INV1) by a fourth transistor (MN11). The output of the inverter is linked to the gates of fifth (MP12) and sixth (MN13) transistors. The fifth transistor (MP12) is connected between the power supply (VDD) and the input of the inverter; the sixth transistor (MN13) is linked to the input of the inverter and to earth via a seventh transistor (MN14); the first clock phase ( phi 1) is applied to the seventh transistor of the input cell and to the second and fourth transistors of the output cell and its complement to the third transistor of the input cell; and the second clock phase ( phi 2) is applied to the second and fourth transistors of the input cell and to the seventh transistor of the output cell and its complement to the third transistor of the output cell. <IMAGE>
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