| 摘要 |
<p>PURPOSE:To save manual adjustment by inverting phase of a clock signal automatically and inputting the signal to a clock terminal of an identification circuit when a change point of a data signal and a leading point of time of the clock signal are close to each other. CONSTITUTION:An AND gate 6 ANDs a clock waveform (d) and a waveform (e), generates a pulse (f) at the leading point of time of a clock signal and an AND gate 7 ANDs an output waveform (c) of an EX-OR 5 and an output waveform (f) of the AND gate 6. Since the phase of a change point of a data signal and a phase at the leading point of time of the clock signal are close to each other, a pulse with a waveform (g) is generated and it is a clock input to a D flip-flop 8. A Q output of the flip-flop 8 is at an L level at application of power, since an H level is inputted to a D input, the Q output goes to an H level by inputting the clock with the waveform (g). A selection circuit 9 selects a B input being an inversed clock signal when an H level is inputted to a selection terminal. Thus, manual adjustment is not required.</p> |
