| 摘要 |
<p>A processor includes a plurality of sets 22 of windowed registers, each set having IN registers and local registers, the IN registers of each set being addressable as the OUT registers of a logically-adjacent preceding set of registers, apparatus for indicating which set of registers is being addressed, a set of global registers which may be addressed with each of the sets of registers, an arithmetic and logic unit 26, a cache memory 28 comprising a number of lines at least equal to the number of registers in an addressable set of windowed registers including the set of global registers and the IN registers of the logically-adjacent set of registers addressable as OUT registers, and apparatus for changing the addresses of lines of the cache holding information presently designated in a particular window register set as information held in OUT registers to addresses designating the IN registers of the next register set, and apparatus for allowing the arithmetic and logic unit to access selected lines of the cache memory as processor registers. <IMAGE></p> |
