| 摘要 |
PURPOSE:To simplify the circuit constitution at a receiver side by stopping the transmission of a transmission data in the unit of bit length of a prescribed transmission data and stopping the edge addition of a clock signal. CONSTITUTION:A serial data DS1 sent from a parallel/serial conversion section A1 is received by a serial/parallel conversion section B1, and a clock signal SC sent from a clock generating section A2 is received by a clock reception section B2, inputted to the serial/parallel conversion section B1, and a parallel data DP2 is outputted from the serial/parallel conversion section B1. When the clock signal SC is not received for a prescribed time, the clock reception section B2 regards it as the end of 5-bit length reception and outputs a load signal Sl2, it is inputted to a data register B3, the parallel data DP2 is loaded to a data register B3, a reception parallel data DP3 is obtained and the signal is reproduced. |
