CLOCK PHASE SETTING CIRCUIT

摘要

PURPOSE:To output a clock signal with a desired phase difference automatically in a range even when the frequency of an input clock signal is changed by generating a clock signal having a phase difference by a period of 1/2 from a phase of the input clock signal automatically. CONSTITUTION:An input clock signal CLKi is counted by a counter CTR and the result of count is fed to delay circuits DL0-DL(n-1). Then the signal CLKi is sequentially retarded by a time tau each and the counter CTR is brought into the holding state when the retarded clock signal is deviated from the input OLKi signal by nearly 1/2 period. Then the output of the counter CTR is shifted at a shifter SIFT by (m-1) bits and the result is fed to the delay circuits DL 0-DL(n-1). Thus, the delay of nearly 1/2 period is grown into a delay of nearly 1/2, and an output clock signal CLKo having a phase difference by a period of 1/2 from a phase of the input clock signal CLKi is generated.