发明名称 SLEEP MODE CONTROL SYSTEM
摘要 <p>PURPOSE:To realize the reduction of power consumption and the increase of data processing speed by inhibiting execution of a sleep mode function when required. CONSTITUTION:A clock switching circuit receives the normal mode clock from a clock switching circuit 11 and the low-frequency sleep mode clock from a clock generator 23, and selects them in accordance with the control signal from a sleep mode discriminating circuit 14. The operation to discriminate a sleep mode set condition by a sleep mode discriminating circuit 14 is permitted or inhibited in accordance with contents of an enable/disable register 31. The operation of the sleep mode discriminating circuit 14 is inhibited or permitted in accordance with data processing contents of a CPU 13 to realize the reduction of power consumption and the increase of the data processing speed.</p>
申请公布号 JPH03116311(A) 申请公布日期 1991.05.17
申请号 JP19890254965 申请日期 1989.09.29
申请人 TOSHIBA CORP 发明人 YAMAKI KAZUNORI
分类号 G06F1/08;G06F1/32;G06F15/78 主分类号 G06F1/08
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