| 摘要 |
<p>PURPOSE:To realize the bit synchronizing circuit against a data input having many jitters by delaying the data, detecting a logical variation of a near-by phase, and finding a phase shifted by (m)=(n-1)/2 only against only one logical variation. CONSTITUTION:A phase detecting circuit 200 for detecting a phase shifted by a delay element portion of an (m)=(n-1)/2 piece portion and holding it as a new latch phase only in the case a variation of only one logical variation point is detected is constituted. In the case only one logical variation is generated, in an output state of exclusive OR circuits 30-33, it is decided that a phase shift is generated, and a latch phase is changed to data of a point shifted by (m)=2. On the other hand, in the case there is no logical variation or in the case there are plural variation points, it is decided to be entirely normal or generation of intermittent jitters and a selected phase is held.</p> |
