| 摘要 |
PURPOSE:To output the data being in phase with a clock of a receiving equipment side by using two pieces of clock signals which are out-of-phase by a quarter period, latching one clock signal at the time of rise or fall of an input signal, and latching the input signal by a selected clock signal. CONSTITUTION:With respect to a clock signal CLK1 being a clock signal of a receiving equipment side, as for a clock signal CLK2, its period is equal and its phase lags by a quarter period, and their occupancy rates are both 50%. In a flip-flop FF1, the clock signal CLK1, and an input signal Din containing timing information are inputted to its data input terminal D, and a clock terminal C, respectively, and by latching the clock signal CLK1 inputted at its rise point, data 1 is outputted. Subsequently, as for a fall and a rise of the input signal Din, a protecting circuit PRT executes no answer, and at the time of a second fall of the input signal Din, the data 1 of an H level is latched, and outputted as data 2. |
