发明名称 CIRCUIT FOR MULTIPLICATION BY 2N
摘要 PURPOSE:To increase the operation speed by using a data memory which divides data to be operated into plural unit data to be operated and stores values obtained by multiplying each unit data to be operated by 2. CONSTITUTION:The product of each unit data C to be operated and 2N is corrected with digit shift value information (g) to obtain a unit operation result (f), and data having the result (f) as lower bits and having digit shift value information (g) as upper bits is stored in a data memory 4. A control part 2 divides data (b) to be operated into unit data (c) to be operated each of which has a prescribed number of digits, and each data (c) is built in an address and is sent to an address lower bit terminal 5b of the data memory 4. Consequently, the unit operation result (f) outputted from the data memory 4 at each time of sending unit data (c) is successively synthesized in serial to obtain the operation result of inputted data (b) to be operated. Since each unit operation result is outputted immediately at the time of input of each unit data to be operated, the operation speed is increased with the required storage capacity of the data memory minimized.
申请公布号 JPH03116325(A) 申请公布日期 1991.05.17
申请号 JP19890254516 申请日期 1989.09.29
申请人 ANRITSU CORP 发明人 MORIMOTO NAOHITO
分类号 G06F7/52;G06F1/02;G06F7/493;G06F7/523;G06F7/53;G06F7/535;G06F7/537 主分类号 G06F7/52
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