发明名称 DATA PROCESSING SYSTEM
摘要 <p>PURPOSE:To shorten the access time to a memory by increasing the pulse width of a clock supplied to a processor in response to the access time required by a storage device. CONSTITUTION:A microprocessor 101 outputs an address signal 203 for execution of an access, and a D-RAM control circuit 104 detects that the signal 203 is aimed at a dynamic memory to produce the control signals 204 and 205 to the dynamic memory and also to send a dividing ratio changing signal 206 to a dividing circuit 107. The circuit 107 switches the 2-dividing ratio to the 4-dividing ratio only for a period when the signal 206 is kept at a low level. As a result, the pulse width of a dividing output waveform 202 is doubled only for the above switching period. Thus the dead time is reduced when an access is given to the memory.</p>
申请公布号 JPH03116253(A) 申请公布日期 1991.05.17
申请号 JP19890253862 申请日期 1989.09.29
申请人 SEIKO EPSON CORP 发明人 NAKAOKA YASUSHI
分类号 G06F12/00;G06F1/04;G06F12/02 主分类号 G06F12/00
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