发明名称 PROCESS AND APPARATUS FOR SYNTHESIZING CIRCUIT DESIGN
摘要 PURPOSE: To shorten the logic synthesis processing time by providing a certain reference used to determine which rule should be first applied. CONSTITUTION: Only model examples concerned at present are designated as VISIBLE model examples, and only rules related to VISIBLE model examples are applied, and model examples which are recently related to rules evaluated as TRUE rules are designated as NEW model examples, and only rules related to NEW model examples are applied. Model examples deleted by application of rules are designated as DELETED model examples, and only rules related to non-DELETED model examples are applied, and correspondence between model examples and rules is divided into groups by a value called SIZEWIN which indicates an effect measure, and the group having the maximum SIZEWIN value is first applied. Thus, the execution time is not unnecessarily extended.
申请公布号 JPH03116384(A) 申请公布日期 1991.05.17
申请号 JP19900169701 申请日期 1990.06.27
申请人 DIGITAL EQUIP CORP <DEC> 发明人 DONARUDO EFU FUUPAA;EDOWAADO JII FUOOTOMIRAA;SUNIIHAMEI KUNDO;DEIBUITSUDO EFU HIRU
分类号 G06F17/50;G06N5/04 主分类号 G06F17/50
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