METHOD FOR FAST RECEIVER LOCKING, UTILIZING ERROR-CORRECTION CODING

摘要

A method for fast frame synchronisation at the receiving end of digital transmission systems is proposed which provides for fast synchronisation even at high bit error rates. For this purpose, it is provided that the data signals are picked up at the output of an FEC decoder (1) designed for two operating modes and are supplied to a circuit (2) synchronising the FEC decoder (1). In the first operating mode, the correction capability of the FEC decoder (1) is switched off; the data are transparently connected through until at least a part of a frame alignment word is detected and a preliminary initial synchronisation is achieved. Then the correction capability of the FEC decoder (1) is switched on and the remainder of the synchronisation process is supported by FEC.