| 摘要 |
<p>A semiconductor memory cell is fabricated on a semicoductor substrate (21) and comprises a switching transistor (23) having a source and drain regions (23a/23b) and covered with a lower inter-level insulating film (25), and a stacked storage capacitor (24) coupled through a contact hole (25a) formed in the lower inter-level insulating film to one of the source and drain regions and having a lower electrode (24a) provided on the lower inter-level insulating film and having a side surface portion, a dielectric film (24b) covering the lower electrode and an upper electrode (24c) covering the dielectric film, in which at least one cave (24ac) is made on the side surface portion so that the amount of surface area and, accordingly, the amount of electric charges accumulated in the stacked storage capacitor are increased even if the stacked storage capacitor occupies a relatively small amount of the real estate.</p> |
