发明名称 CLOCK SYNCHRONOUS NETWORK AND DATA COMMUNICATION
摘要 PURPOSE: To process data whose phase is arbitrarily different from that of a system clock transmitted form a subscriber station by providing an exchange with a delay line, which receives an input data cell and selecting a tap, which keeps the most suitably synchronized data with a master clock, from different taps of a delay line. CONSTITUTION: A central exchange 1 transfers packets of data to subscriber stations 3 at a rate determined by a master clock 5. Each subscriber station 3 uses normal PLL to reproduce the master clock from received data packets and returns data to the central exchange 1 with its frequency. The central exchange 1 has a phase alignment system on the reception side. The phase alignment system is provided with a delay line 7 for reception of input data and an eye position detection circuit 9 and uses the delay line 7 to gradually delay data and specifies the tap, which has data of a phase suitable for the master clock, from the delay line 7.
申请公布号 JPH03113928(A) 申请公布日期 1991.05.15
申请号 JP19900032302 申请日期 1990.02.13
申请人 BRITISH TELECOMMUN PLC <BT> 发明人 JIYON UIRIAMU BARANSU
分类号 H04B10/20;H04L7/00;H04L7/033;H04L7/04;H04L12/56;H04Q11/04 主分类号 H04B10/20
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