| 摘要 |
<p>An adaptive gate discharge circuit for discharging the gate of a power FET transistor. The adaptive gate discharge circuit includes discharge driver circuitry which responds to the control signal by discharging the power FET gate from the initial "on" potential of the power FET to below a selected potential at which the power FET is turned off. During gate discharge, but prior to the potential of the power FET gate dropping below the selected potential, adaptive bias circuitry continues to operate to provide biasing current both to the discharge driver circuitry as well as to any other circuitry it may be biasing. However, when the potential of the power FET gate drops below the selected potential, low current biasing circuitry reduces the operating voltage of the adaptive biasing circuitry thereby turning off the adaptive biasing circuitry and any other circuitry it may be biasing.</p> |
