Parallel processing system including control computer for dividing an algorithm into subalgorithms and for determining network interconnections

摘要

The device 10 comprises a large number of transputers T1 to T16 (only T1 and T16 are shown), Tmem, Tx, Ty, Tz, Tt. These are divided into a set of working transputers T1 to T16, and a set of interface transputers Tx, Ty, Tz, Tt providing input/output facilities for the device, both sets being under the control of a transputer Tmem. The transputer Tmem receives instructions for the device and breaks them down into programs for parallel processing by the transputers T1 to T16. These transputers will normally need to communicate, and the necessary connections are provided by a switch network 12, under the control of the transputer Tmem. The programs are so allocated to the transputers T1 to T16 and the switch network 12 is so arranged that direct connections are provided between any transputers which must communicate for the execution of their respective programs. Other connection arrangements are described, including a universal circuit capable of connecting the transputers T1 to T16 to form any theoretically possible network.